SCOPE XITE-1: new DSP hardware from Sonic Core!

FrancisHarmany · Post by **FrancisHarmany** » Thu Mar 13, 2008 9:11 am

So can I run both the Scope & Xite on one system ?

Just ADAT from Xite <> SCOPE or something ?

Post by **hubird** » Thu Mar 13, 2008 9:13 am

if SFP is able to 'read' different PCI-e slots altogether - just like it does read PCI slots now - this could be possible indeed:-)

FrancisHarmany · Post by **FrancisHarmany** » Thu Mar 13, 2008 9:19 am

hubird wrote:if SFP is able to 'read' different PCI-e slots altogether - just like it does now - this could be possible indeed:-)

Ok so this way people could have more outs on their system ? Then we can buy up old cards and have more IO.......

So if I route adat-in to some output it wouldnt hurt my pci bandwidth either right ?!

Post by **hubird** » Thu Mar 13, 2008 9:30 am

I'm just guessing and hoping... the combination of PCI and PCI-e in one comp could lead to unexpected troubles i.e.
on OSX there's no chance at all of course.

alfonso · Post by **alfonso** » Thu Mar 13, 2008 10:19 am

FrancisHarmany wrote:So can I run both the Scope & Xite on one system ?

Just ADAT from Xite <> SCOPE or something ?

I'm not directly informed, but I'd say that a single Scope software can only use cards that are interconnected in a single environment....like if you have 2 PCI cards without stdm connection the system is broken.

If you have, instead a PC with it's own Scope cards and a laptop with Xcite-1, then you can connect all the adat, spidif and midi ports to benefit of 2 environments, like it is now with two Scope machines.

ScofieldKid · Post by **ScofieldKid** » Fri Mar 14, 2008 12:35 am

Just catching up on this thread... sorry if I'm repeating.

Just guessing, but I suspect we will have much better overhead in this design.

For example, if we are going from a design that was built with 32-bits and 33MHz at the heart of it.... and now we are in a place where the internals could easily be 64-bit and 200MHz, we should be in a better place. Since there are PCI-X to PCIE bridges, we may have just gotten a leap from old-style PCI to full-on PCI-X.

Again, this is all speculation, but I wouldn't be surprised if they optimized when they were designing this to take advantage of the faster speed capabilities of the new DSP's.

See also: http://www.analog.com/communities/audio ... mWare.html

NOTE: I'm sure someone mentioned it before, but note that PCIE is full-duplex, and serial. This will be a much more capable communication channel than the old-school PCI we have been wrestling with.

[ Ah, I see you guys already ran 100+ MasterVerbs.... As Emily Littella would say, "Nevermind"!

]

spacef · Post by **spacef** » Sat Mar 15, 2008 3:37 am

i am trying to put a dual core in my pentium II mother board... tss, something not worlking

BingoTheClowno · Post by **BingoTheClowno** » Sat Mar 15, 2008 3:59 am

ScofieldKid wrote:
NOTE: I'm sure someone mentioned it before, but note that PCIE is full-duplex, and serial. This will be a much more capable communication channel than the old-school PCI we have been wrestling with.

Well, the PCI is 32 bit wide working at 133MB/s, I don't think that speed was the issue.

spacef · Post by **spacef** » Sat Mar 15, 2008 4:06 am

Well, the PCI is 32 bit wide working at 133MB/s, I don't think that speed was the issue.

the old pci is shared with other peripherals and was a major cause of bottleneck (look for "southbridge" and evolution of pci / pci-e or benchmarks). the pci-e improvements has to be combined with improvements in how the motherboard manages other internal and external peripherals. I am not a specialist, but going to pci-e seems that it will deliver more than just the difference between pci and pci-e due to the fact that many peripheral, that used to use the pci bus, don't use it anymore, according to readings about x86 and new motherboard architecture (in which i am not a specialist)...
In this respect, I am SO glad they didn't go firewire, so many of my MAC friends fried them all (FW direct mobo connections) and so easily....

BingoTheClowno · Post by **BingoTheClowno** » Sat Mar 15, 2008 5:15 am

I'm not an expert either, but according to this article, PCIe uses the point to point SWITCH topology.

What I get from this is that you will be able to use only ONE PCIe card at the time. In other words you won't be able to stack multiple cards as was the case with the PCI cards. Some one please confirm this.
So my next question would be, how many DSP chips are in the Xcite box?

voidar · Post by **voidar** » Sat Mar 15, 2008 5:40 am

No problem, as the xcite-box is expandable.

Shayne White · Post by **Shayne White** » Sat Mar 15, 2008 5:43 am

BingoTheClowno wrote:I'm not an expert either, but according to this article, PCIe uses the point to point SWITCH topology.

What I get from this is that you will be able to use only ONE PCIe card at the time. In other words you won't be able to stack multiple cards as was the case with the PCI cards. Some one please confirm this.
So my next question would be, how many DSP chips are in the Xcite box?

I'm pretty sure that's not the case -- otherwise, motherboards would only include one PCI-E slot!

PCI-E cards use separate "lanes" (channels) to the chipset, whereas PCI had one connection to the chipset that all the cards shared. That's the big difference between parallel and serial.

As for Scope, that fact that the Xite has an "XTDM" connection means you will be able to use multiple boxes together, I'm thinking.

Shayne

voidar · Post by **voidar** » Sat Mar 15, 2008 8:23 am

Think of it as PCI-latency and IRQ.

Only one PCI-e device gets attention at a given place in time. The Xcite-1 is a scalable PCI-e device.

BingoTheClowno · Post by **BingoTheClowno** » Sat Mar 15, 2008 9:41 am

In order to transmit PCIe packets, which are composed of multiple bytes, a one-lane link must break down each packet into a series of bytes, and then transmit the bytes in rapid succession. The device on the receiving end must collect all of the bytes and then reassemble them into a complete packet. This disassembly and reassembly happens must happen rapidly enough to where it's transparent to the next layer up in the stack. This means that it requires some processing power on each end of the link. The upside, though, is that because each lane is only one byte wide, very few pins are needed to transmit the data. You might say that this serial transmission scheme is a way of turning processing power into bandwidth; this is in contrast to the old PCI parallel approach, which turns bus width (and hence pin counts) into bandwidth. It so happens that thanks to Moore's Curves, processing power is cheaper than bus width, hence PCIe's tradeoff makes a lot of sense.

http://arstechnica.com/articles/paedia/ ... pcie.ars/5

spacef · Post by **spacef** » Sat Mar 15, 2008 10:00 am

http://www.tomshardware.com/2007/03/27/ ... page2.html

PCI Express is a bi-directional point-to-point link, meaning that it offers the same bandwidth in both directions, and does not need to share its bandwidth with other devices, as is the case with parallel PCI.

x1 PCI Express mode provides a bandwidth of 256 MB/s upstream and downstream.

(that's 2*256 Mb/s (full duplex))

ScofieldKid · Post by **ScofieldKid** » Sat Mar 15, 2008 10:20 pm

At a minimum, I think we are 4-times the bandwidth in the new setup. Which is an awesome thing.

But the point is moot. The testers have already proven that we have a massive improvement. So it's off to the races. I can forsee doing a lot of massive projects on this thing.

Shroomz~> · Post by **Shroomz~>** » Sat Mar 15, 2008 10:23 pm

This sounds amazing. Thanks for the messe feedback guys!

Btw, I too am a fan of a Z-link version = 16 channels @24/96.

Mary Mungo · Post by **Mary Mungo** » Mon Mar 17, 2008 12:51 pm

Can anybody buy me one, please

firubbi · Post by **firubbi** » Sun Apr 20, 2008 10:01 am

today is 20th april....whats the current update.
only 10 days left

Shayne White · Post by **Shayne White** » Sun Apr 20, 2008 12:18 pm

You mean 40 days left. SC has until 11:59pm on May 31st before they miss their deadline. I sure hope it IS beginning of May rather than late May. On the other hand, we want them to work out all the bugs before release.